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ordering number : enn * 6526 63000rm (ot) no. 6526-1/38 overview the lc74731w and lc74732w are on-screen display cmos ics that display characters and patterns on a tv screen under the control of a microcontroller. these ics display 16 16-dot characters and up to 12 lines of text with 24 characters per line. features text structure: 12 lines 24 characters (up to 288 characters) character format: 16 16 dots character display clock frequency: about 9 mhz character sizes: four sizes each in the horizontal and vertical directions with the size set in line units. number of characters supported: lc74731w:256 (internal) lc74732w:512 (internal) up to 8192 using an external rom (for japanese) [reference] jis x0298 (1990): 6877 characters jis level 1 kanji: 2965 characters jis level 2 kanji: 3388 characters special characters: 524 characters display start positions: 128 positions each in the horizontal and vertical directions blinking, reverse video, reversed blinking, and character outlining: may be specified in individual character units. blinking types: two types with periods of about 1.0 and about 0.5 seconds. blanking: the whole font area (16 16 dots) can be blanked in line units (four types: no blanking, character size blanking, character plus outlining size blanking, and whole area up to adjacent character blanking) line spacing control: zero to seven scan lines, in line units character color: eight colors in character units (in internal synchronization mode): 2 fsc and 4 fsc (black, red, green, yellow, blue, magenta, cyan, and white) character background color: eight colors (in internal synchronization mode): 2 fsc and 4 fsc (black, red, green, yellow, blue, magenta, cyan, and transparent) screen background color: eight colors (in internal synchronization mode): 2 fsc and 4 fsc (black, red, green, yellow, blue, magenta, cyan, and white) external control inputs: serial interface with an 8-bit data size. built-in sync separator circuit video outputs: ntsc, pal, palm, paln, ntsc 4.43, and pal 60 composite video signal outputs supports y/c input package dimensions preliminary lc74731w,74732w sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan on-screen display controller cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. 10.0 12.0 1.25 0.5 1.25 1.25 0.5 1.25 0.18 12.0 116 17 32 33 48 49 64 10.0 0.5 1.7max 0.5 0.1 0.15 sanyo: sqfp64 [lc74731w,74732w]
pin assignment no. 6526-2/38 lc74731w,74732w 1 v ss 1 48 a6 2 xtalin 47 a7 3 xtalout 46 a8 4 ctrl1 45 a9 5 oscin 44 a10 6 oscout 43 a11 7 mute 42 a12 8 cdlr 41 a13 9 syncjdg/rout 40 a14 10 chara/gout 39 a15 11 blank/bout 38 a16 12 ieout/blkout 37 a17 13 outmod 36 v dd 1 14 cs 35 rst 15 sin (v) 34 sepin 16 sclk 33 sepout (h) cout cin -nc- -nc- v ss 2 -nc- cvcr synin v dd 2 -nc- cbias yout yin cvout cvin hftin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 d1 62 d2 61 d3 60 d4 59 d5 58 d6 57 d7 56 ce 55 oe 54 a0 53 a1 52 a2 51 a3 50 a4 49 a5 64 d0
no. 6526-3/38 lc74731w,74732w pin functions pin no. pin function description 1v ss 1 ground ground connection. (digital system ground) 2 xtalin crystal oscillator connections connections for the crystal element and capacitors that form the internal sync signal generating 3 xtalout crystal oscillator. xtalin can also be used to input an external clock signal. (2fsc or 4fsc) 4 ctrl1 switches the crystal oscillator selects external clock input mode or crystal oscillator mode. low: crystal oscillator mode, hig h: input external clock input mode. 5 oscin lc oscillator connections connections for the coil and capacitor that form the character output dot clock generation oscillator. 6 oscout this is an active-low input with hysteresis characteristics (more+). when low, the 7 mute muting control input cvout, yout, and cout outputs are set to either, (1) csync, csync, pe, or (2) pe pe, pe. in the initial state, (1) is selected. this setting is switched by commands. 8 cdlr background color phase connection for the resistor used to adjust the background color phase adjustment outputs the result of the judgment as to whether or not the external sync signal is present. 9 syncjdg external sync signal judgment a high level is output when a sync signal is present. /rout output (rout output) the dot clock (lc oscillator) is output when rst is low. (the ic can be set up to not output this signal during resets by commands.) 10 chara/gout character output character signal output (gout output) 11 blank/bout blank output (bout output) blank signal output pin 12 ieout/blkout internal/external output internal synchronization (high)/external synchronization (low) state output pin (blkout output) 13 outmod output switching input switches between output from pins 9 to 12 and input to pin 32. low: normal operation, high: rgb output supported serial data input enable 14 cs enable input serial data input is enabled when low. more+ (hysteresis input characteristics) 15 sin data input serial data input more+ (hysteresis input characteristics) 16 sclk clock input serial data input clock input more+ (hysteresis input characteristics) 17 v dd 2 power supply composite video signal level adjustment power supply. (analog system power supply) 18 cout color signal output color (c) signal output 19 nc this pin must either be left open or connected to ground. 20 cin color signal input color (c) signal input 21 cbias chrominance bias output chrominance signal bias level output 22 nc this pin must be either left open or connected to ground. 23 yout luminance signal output luminance signal (y) output 24 nc this pin must be either left open or connected to ground. 25 yin luminance signal input luminance signal (y) input 26 v ss 2 ground ground 27 cvout video signal output composite video signal output 28 nc this pin must either be left open or connected to ground. 29 cvin video signal input composite video signal input 30 cvcr video signal input secam chrominance signal input 31 hftin halftone signal input halftone signal input 32 synin sync separator circuit input video signal input to the internal sync separator circuit 33 sepout composite sync signal output composite sync signal output from the internal sync separator circuit 34 sepin vertical sync signal input vertical sync signal input more+ (hysteresis input characteristics) 35 rst reset input system reset input a built-in pull-up resistor can be included in this pin? input circuit. (hysteresis input characteristics) 36 v dd 1 power supply (+5 v) power supply (+5 v: digital system power supply) continued on next page.
no. 6526-4/38 lc74731w,74732w continued from preceding page. pin no. pin function description 37 a17 address output 17 rom address output 17 38 a16 address output 16 rom address output 16 39 a15 address output 15 rom address output 15 40 a14 address output 14 rom address output 14 41 a13 address output 13 rom address output 13 42 a12 address output 12 rom address output 12 43 a11 address output 11 rom address output 11 44 a10 address output 10 rom address output 10 45 a9 address output 9 rom address output 9 46 a8 address output 8 rom address output 8 47 a7 address output 7 rom address output 7 48 a6 address output 6 rom address output 6 49 a5 address output 5 rom address output 5 50 a4 address output 4 rom address output 4 51 a3 address output 3 rom address output 3 52 a2 address output 2 rom address output 2 53 a1 address output 1 rom address output 1 54 a0 address output 0 rom address output 0 55 oe output enable rom output enable output. this is an active-low output. 56 ce chip enable rom chip enable output. this is an active-low output. 57 d7 data input 7 rom data input 7. more+ (hysteresis input characteristics) 58 d6 data input 6 rom data input 6. more+ (hysteresis input characteristics) 59 d5 data input 5 rom data input 5. more+ (hysteresis input characteristics) 60 d4 data input 4 rom data input 4. more+ (hysteresis input characteristics) 61 d3 data input 3 rom data input 3. more+ (hysteresis input characteristics) 62 d2 data input 2 rom data input 2. more+ (hysteresis input characteristics) 63 d1 data input 1 rom data input 1. more+ (hysteresis input characteristics) 64 d0 data input 0 rom data input 0. more+ (hysteresis input characteristics)
no. 6526-5/38 lc74731w,74732w specifications maximum ratings at ta = 25? parameter symbol conditions ratings unit min max supply voltage v dd v dd 1 and v dd 2v ss ?0.3 v ss + 6.5 v input voltage v in all input pins v ss ?0.3 v dd 1 + 0.3 v output voltage v out syncjdg, blank, chara, sepout, a0 to a17, v ss ?0.3 v dd 1 + 0.3 v ce, and oe allowable power dissipation pdmax 275 mw operating temperature topr ?0 +70 ? storage temperature tstg ?0 +125 ? parameter symbol conditions ratings unit min typ max supply voltage v dd 1v dd 1 4.5 5.0 5.5 v v dd 2v dd 2 4.5 5.0 6.5 v supply voltage v dd 1v dd 1 2.7 5.0 5.5 v [only for rgb output] v dd 2v dd 2 2.7 5.0 6.5 v v ih 1 cs, sin, sclk, sepin, and mute 0.8 v dd 1 5.5 v high-level input voltage v ih 2 rst 0.8 v dd 1 v dd 1 + 0.3 v v ih 3 ctrl1 and outmod 0.7 v dd 1 v dd 1 + 0.3 v v ih 4 d0 to d7 0.8 v dd 1 5.5 v v il 1 rst, cs, sin, sclk, sepin, and mute v ss ?0.3 0.2 v dd 1 v low-level input voltage v il 2 ctrl1 and outmod v ss ?0.3 0.3 v dd 1 v v il 3 d0 to d7 v ss ?0.3 0.2 v dd 1 v pull-up resistor r pu rst, cs, sin, sclk, and mute (when the pull-up 25 50 90 k resistor option is specified) composite video signal input v in 1 cvin and cvcr v dd 1 = 5 v 2.0 vp-p voltage v in 2 synin v dd 1 = 5 v 1.5 2.0 2.5 vp-p input voltage v in 3 xtalin (when an external clock input is used) v dd 1 = 5 v 5.0 vp-p fin = 2 fsc, 4 fsc the xtalin and xtalout oscillator pins (2 fsc: ntsc) 7.159 mhz f osc1 the xtalin and xtalout oscillator pins (4 fsc: ntsc) 14.318 mhz oscillator frequency the xtalin and xtalout oscillator pins (2 fsc: pal) 8.867 mhz the xtalin and xtalout oscillator pins (4 fsc: pal) 17.734 mhz f osc2 the oscin and oscout oscillator pins (lc oscillator) 10 mhz recommended operating conditions note: if the xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measu res.
no. 6526-6/38 lc74731w,74732w parameter symbol pin conditions ratings unit min typ max input off leakage current ileak1 cv in , cv cr , c in , and y in 1a output off leakage current ileak2 cv out , c out , and y out 1a v oh 11 syncjdg, setpout, v dd 1 = 5.5 to 4.5 v 0.9 v dd 1v blank, chara, and ieout i oh = ?.0 ma v oh 12 syncjdg, setpout, v dd 1 = 4.4 to 2.7 v 0.9 v dd 1v high-level output voltage blank, chara, and ieout i oh = ?.5 ma v oh 21 a0 to a17, oe, and ce v dd 1 = 5.5 to 4.5 v 0.9 v dd 1v i oh = ?.0 ma v oh 22 a0 to a17, oe, and ce v dd 1 = 4.4 to 2.7 v 0.9 v dd 1v i oh = ?.5 ma v ol 11 syncjdg, sepout, v dd 1 = 5.5 to 4.5 v 0.1 v dd 1v blank, chara, and ieout i ol = 1.0 ma v ol 12 syncjdg, sepout, v dd 1 = 4.4 to 2.7 v 0.1 v dd 1v low-level output voltage blank, chara, and ieout i ol = 0.5 ma v ol 21 a0 to a17, oe, and ce v dd 1 = 5.5 to 4.5 v 0.1 v dd 1v i ol = 1.0 ma v ol 22 a0 to a17, oe, and ce v dd 1 = 4.4 to 2.7 v 0.1 v dd 1v i ol = 0.5 ma i ih rst, cs, sin, sclk, ctrl1, v in = v dd 11a input current mute, and outmod i il cs, sin, sclk, ctrl1, and v in = v ss 1 1a outmod all outputs: open operating current drain i dd 1v dd 1 xtal: 17.734 mhz 40 ma lc: 10 mhz i dd 2v dd 2v dd 2 = 5 v 20 ma electrical characteristics at ta = ?0 to +70?, v dd 1 = 5 v unless otherwise specified. continued on next page.
no. 6526-7/38 lc74731w,74732w parameter symbol pin conditions ratings unit min typ max (1) 0.80 sync level v sn (2) 1.00 v (3) 1.40 (1) 1.37 pedestal level v pd (2) 1.57 v (3) 1.97 (1) 1.07 color burst low level v cbl (2) 1.27 v (3) 1.67 (1) 1.67 color burst high level v cbh (2) 1.87 v (3) 1.27 cvout (1) 1.23 background color 1 low level v rsl 1 (1): when sync ?level = 0.8 v v dd 1 = 5.0 v (2) 1.43 v (2): when sync ?level = 1.0 v v dd 2 = 5.0 v (3) 1.83 (3): when sync ?level = 1.4 v (1) 2.37 background color 1 high level v rsh 1 (2) 2.57 v (3) 2.97 (1) 1.52 background color 2 low level v rsl 2 (2) 1.72 v (3) 2.12 (1) 2.01 background color 2 high level v rsh 2 (2) 2.21 v (3) 2.61 (1) 1.50 outlining level 1 v bk 1 (2) 1.70 v (3) 2.10 (1) 1.80 outlining level 2 v bk 2 (2) 2.00 v (3) 2.40 (1) 2.08 outlining level 3 v bk 3 (2) 2.28 v (3) 2.68 (1) 2.65 character level 1 v cha 1 (2) 2.85 v (3) 3.25 (1) 2.23 character level 3 v cha 3 (2) 2.43 v (3) 2.83 continued from preceding page.
supplementary materials figure 1 osd serial data input timing no. 6526-8/38 lc74731w,74732w t w (cs) cs t su (cs) t w (sclk) t w (sclk) t h (cs) sclk t su (sin) t h (sin) sin t word t wt sclk 01 567 01 5 467 cs parameter symbol conditions ratings unit min typ max minimum input pulse width t w (sclk) sclk 200 ns t w (cs) cs (the period when cs is high) 1 s data setup time t su (cs) cs 200 ns t su (sin) sin 200 ns data hold time t h (cs) cs 2 s t h (sin) sin 200 ns one word write time t word the time to write 8 bits of data 4.2 ? t wt ram data write time 1 s osd write (see figure 1.) at ta = ?0 to +70?, v dd 1 = 5 0.5 v
system block diagram no. 6526-9/38 lc74731w,74732w osc in sync jdg rst outmod ieout blank chara mute sclk sin cs sep c sep out osc out sep in syn in vdd1, vdd2 vss1, vss2 cv out cdlr c in cbias yout yin cv in ctrl1 xtal in xtal out cvcr cout serial to parallel converter character output dot clock oscillator synchronous judgment composite sync separator control sync separator circuit 8-bit latch and command decoder horizontal character size register horizontal size counter vertical size counter timing generator horizontal dot counter horizontal display position detection vertical display position detection character control counter sync signal generator character output control background control video output control line control counter vertical dot counter blinking and reverse video control circuit vertical character size register horizontal display position register vertical display position register blinking and reverse video control register display control register ram write address counter display ram decoder font rom shift register decoder a0 to a17, oe, ce d0 to d7
no. 6526-10/38 lc74731w,74732w display control commands display control commands display control commands have an 8-bit format and are transferred using the serial input function. commands consist of a command identification code in the first byte and command data in the following bytes. first byte second byte command command identification code data data 7654321076543210 command0 1000v3v2v1v0000h4h3h2h1h0 (write address setup) at2 at1 cb2 cb1 cb0 cc2 cc1 cc0 command1 (character write) 1001irsd2sd1sd0000c12c11c10c9c8 c7 c6 c5 c4 c3 c2 c1 c0 command20 101000 rrm1 rrm0 0 vp6 vp5 vp4 vp3 vp2 vp1 vp0 (vertical display start position) command21 101001000hp6hp5hp4hp3hp2hp1hp0 (horizontal display start position) command22 1010100srm0000vs1vs0hs1hs0 (character size) command23 1010110 lszud 00 lszb5 lsza4 lsz93 lsz82 lsz71 lsz60 (character size - in line units) command3 1011 tstmod ramers oscstp sysrst 0 lcsoff xn53s blksel lc fs bk dspon (display control) command4 1100np2np1np0i/n0 hlfint bcl1 bcl0 cb ph2 ph1 ph0 (display control) command50 110100 dislin i/e 0 rn2 rn1 rn0 sn3 sn2 sn1 sn0 (sync signal detection 1) command51 110101 mut1 mut0 0 o rne0 sjn3 sjn2 sjn1 sjc1 sjc0 (sync signal detection 2) command52 110110 evebss lspss 0 cinsel cinctl vnpsel vspsel mskers msksel eglsel (display control) command53 110111 rslg1 rslg0 00 ctl3 sposel palal4 ihsel vssel hssel (display control) command60 1110000brm0 bxblv1 bxblv0 bxwlv1 bxwlv0 atsel blk1 blk0 (outlining setting) coomand61 1110010 lfcud 00 lfcb5 lfca4 lfc93 lfc82 lfc71 lfc60 (outlining setting - in line units) command62 1110100grm0o bxc1 gs1 gs0 gy2 gy1 gy0 (line spacing) command63 1110110 lgyud 00 lgyb5 lgya4 lgy93 lgy82 lgy71 lgy60 (line spacing - in line units) command70 1111000lrm00 bklc1 bklc0 chlc1 chlc0 rslc1 rslc0 (display level) command71 1111010 lclud 00 lclb5 lcla4 lcl93 lcl82 lcl71 lcl60 (display level - in line units) command72 111110 lhtdat lhtud 00 lhtb5 lhta4 lht93 lht82 lht71 lht60 (halftone - in line units) command73 111111000 dasss gbsel outsel hspsw xonss blk01 blk00 (rgb control) note that when the display character data write command (command1) is written, tthese ics lock into the display character data write mode, and another first byte cannot be written. when the cs pin is set high, the these ics are set to the command0 (display memory write address setup mode) state.
command0 (display memory write address setup command) no. 6526-11/38 lc74731w,74732w first byte da0 to 7 register content notes state function 7 1 command 0 identification code 6 0 display memory write address setup 50 40 3v3 0 display memory line address (0 to b (hexadecimal)) 1 2v2 0 1 1v1 0 1 0v0 0 1 second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification code 60 50 4h4 0 display memory line address (0 to 17 (hexadecimal)) 1 3h3 0 1 2h2 0 1 1h1 0 1 0h0 0 1
no. 6526-12/38 lc74731w,74732w command1 (display character data write setup command) first byte da0 to 7 register content notes state function 71 6 0 command 1 identification code 5 0 display character data write settings 41 3ir 0 internal rom switching between internal and external rom 1 external rom 2 sd2 0 white-on-black (convex) display character frame specification 1 black-on-white (concave) display 1 sd1 0 character frame start: off 1 character frame start: on 0 sd0 0 character frame stop: off 1 character frame stop: on second byte (1) da0 to 7 register content notes state function 0 character attribute 2: off blinking specification 7 at2 (character frame upper side: off) selected by com60 second byte and atsel. 1 character attribute 2: on (character frame upper side: on) 0 character attribute 1: off reverse video specification 6 at1 (character frame lower side: off) selected by com60 second byte and atsel. 1 character attribute 1: on (character frame lower side: on) 5 cb2 0 cb2 cb1 cb0 character background color character background color specification 1(b g r) 4 cb1 0 0 0 0 black 1 0 0 1 red 0 0 1 0 green 0 1 1 yellow 3 cb0 1 0 0 blue 1 1 0 1 magenta 1 1 0 cyan 1 1 1 transparent 2 cc2 0 cc2 cc1 cc0 character color character color specification 1(b g r) 1 cc1 0 0 0 0 black 1 0 0 1 red 0 0 1 0 green 0 1 1 yellow 0 cc0 1 0 0 blue 1 1 0 1 magenta 1 1 0 cyan 1 1 1 white note that when this command is input, the lc74731w/74732w lock into the display character data write mode until the cs pin is set high.
no. 6526-13/38 lc74731w,74732w second byte (2) da0 to 7 register content notes state function 70 60 50 4 c12 0 character code (00xx to 1fxx (hexadecimal)) external rom upper address 1 3 c11 0 1 2 c10 0 1 1 c09 0 1 0 c08 0 1 second byte (3) note that all registers are set to 0 when these ics are reset by the rst pin. continuous mode (cleared by setting cs high) operates as follows according to ir. when internal rom is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-3 1-2-3 1-2-3 when external rom is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-2 1-2-3 1-2-2 1-2-3 note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 c07 0 character code (00 to ff (hexadecimal)) external rom lower address 1 fe (hexadecimal): space character internal rom address 6 c06 0 ff (hexadecimal): transparent space character 1 5 c05 0 1 4 c04 0 1 3 c03 0 1 2 c02 0 1 1 c01 0 1 0 c00 0 1
no. 6526-14/38 lc74731w,74732w command20 (vertical display start position setup command) first byte da0 to 7 register content notes state function 7 1 command 2 identification code 6 0 vertical display position and vertical direction character size 5 1 settings 40 3 0 extended command 0 identification code 20 1 rrm1 0 rrm1 rrm0 continuous ram write mode specification 1 0 0 initial value (depends on ir) 0 0 1 1-2-1 1-2-2 1-2-3 fixed 0 rrm0 1 1 0 1-2-2 1-2-3 fixed 1 1 1-2-3 fixed second byte da0 to 7 register content notes state function 7 0 second byte identification bit 6 vp6 0 if vs is the vertical display start position then: the vertical display start position is set by the 7 bits (msb) 1 vp0 to vp6. 5 vp5 0 the weight of bit 1 is 2h. 1 h: the horizontal synchronization pulse period 4 vp4 0 a = 20h (525h systems) 1 = 25h (625h systems) 3 vp3 0 1 2 vp2 0 1 1 vp1 0 1 0 vp0 0 (lsb) 1 6 vs = a + h (2 2 n vpn) n=0 hsync hs vs character display area vsync
no. 6526-15/38 lc74731w,74732w command21 (horizontal display start position setup command) first byte da0 to 7 register content notes state function 7 1 command 2 identification code 6 0 horizontal display position setup and horizontal direction 5 1 character size settings 40 3 0 extended command 1 identification code 21 10 00 second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 hp6 0 if hs is the horizontal start position then: the horizontal display start position is set by the 7 (msb) 1 bits hp0 to hp6. 5 hp5 0 the weight of bit 1 is 2tc. 1 4 hp4 0 tc: period of the oscillator connected to oscin/oscout in 1 operating mode. 3 hp3 0 1 2 hp2 0 1 1 hp1 0 1 0 hp0 0 (lsb) 1 6 hs =tc (2 2 n hpn) n=0
no. 6526-16/38 lc74731w,74732w command22 (character size setting command) first byte da0 to 7 register content notes state function 7 1 command 2 identification code 6 0 horizontal display position setup and horizontal direction 5 1 character size settings 40 3 1 extended command 2 identification code 20 10 0 srm 0 continuous mode: off character size continuous mode specification 1 continuous mode: on second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 50 40 3 vs1 0 vs1 vs0 character size vertical direction character size, in line units 100 1 001 2 2 vs0 1 10 3 11 4 1 hs1 0 hs1 hs0 character size horizontal direction character size, in line units 100 1 001 2 0 hs0 1 10 3 11 4
no. 6526-17/38 lc74731w,74732w command23 (character size and line setup command) first byte da0 to 7 register content notes state function 7 1 command 2 identification code 6 0 horizontal display position setup and horizontal direction 5 1 character size settings 40 3 1 extended command 3 identification code 21 10 0 lszud 0 lower lines: 0 to 5 (hexadecimal) upper/lower line specification 1 upper lines: 6 to b (hexadecimal) second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 lszb5 0 line 6 (line 12) specification: off the line shown in parentheses is specified when 1 line 6 (line 12) specification: on lszud is 1. 4 lsza4 0 line 5 (line 11) specification: off 1 line 5 (line 11) specification: on 3 lsz93 0 line 4 (line 10) specification: off 1 line 4 (line 10) specification: on 2 lsz82 0 line 3 (line 9) specification: off 1 line 3 (line 9) specification: on 1 lsz71 0 line 2 (line 8) specification: off 1 line 2 (line 8) specification: on 0 lsz60 0 line 1 (line 7) specification: off 1 line 1 (line 7) specification: on
no. 6526-18/38 lc74731w,74732w command3 (display control setup command) first byte da0 to 7 register content notes state function 7 1 command 3 identification code 6 0 display character data write settings 51 41 3 tstmod 0 normal operating mode this bit must always be 0. 1 test mode 2 ramers 0 the ram erase operation takes about 500 ?. (it 1 erase display ram (sets the data to ff (hexadecimal)) must be executed in the dspoff state.) 1 oscstp 0 do not stop the crystal and lc oscillator circuits. this setting is valid in external synchronization 1 stop the crystal and lc oscillator circuits. mode when character display is off. 0 sysrst 0 the reset occurs when the cs pin is low, and is 1 reset all registers. this turns the display off. cleared when cs is set high. second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 lcsoff 0 normal operation switches the lc oscillator stop control 1 lc oscillator stop: disabled 5 xn53s 0 normal switches the crystal oscillator capability 1 switching 4 blksel 0 character display area specifies the character size that fills the whole 1 video display area character area. 3lc 0 the lc oscillator is used as the dot clock. selects the dot clock used for character display in 1 the crystal oscillator is used as the dot clock. the horizontal direction. 2fs 0 crystal oscillator frequency: 2 fsc sets the crystal oscillator frequency. 1 crystal oscillator frequency: 4 fsc 1bk 0 blinking period: 0.5 s switches the blinking period. 1 blinking period: 1 s 0 dspon 0 character display: off 1 character display: on
no. 6526-19/38 lc74731w,74732w command4 (display control setup command) first byte da0 to 7 register content notes state function 7 1 command 4 identification code 6 1 display control settings 50 40 3 np2 0 np2 np1 np0 signal format switches the signal format 1 0 0 0 ntsc 2 np1 0 0 0 1 pal-m 1 0 1 0 pal 0 0 1 1 pal-n 1 np0 1 1 0 0 ntsc4.43 1 0 1 pal60 0 i/n 0 interlaced switches between interlaced and noninterlaced 1 noninterlaced second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 hlfint 0 normal mode 1 semi-internal synchronization mode 5 bcl1 0 bcl1 bcl0 only valid in internal synchronization mode. 1 0 0 background color shown 0 0 1 no background color (rsl1) 4 bcl0 1 1 0 no background color (cbh) 1 1 no background color (rsh1) 3cb 0 the color burst signal is output. only valid when bcl is high. 1 color burst signal output is stopped. 2 ph2 0 ph2 ph1 ph0 background color background color specification 1bgr 1 ph1 0 0 0 0 black (rslx) 1 0 0 1 red 0 0 1 0 green 0 1 1 yellow 0 ph0 1 0 0 blue 1 1 0 1 magenta 1 1 0 cyan 1 1 1 white (rshx)
no. 6526-20/38 lc74731w,74732w command50 (sync signal detection 1 setup command) first byte da0 to 7 register content notes state function 7 1 command 5 identification code 6 1 sync signal control settings 50 41 3 0 extended command 0 identification code 20 1 dislin 0 12 lines switches the number of lines displayed. 1 10 lines 0 i/e 0 external synchronization switches between internal and external 1 internal synchronization synchronization second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 rn2 0 rn2 rn1 rn0 number of times hsync detected 1 0 0 0 0 times (32 times) 5 rn1 0 0 0 1 4 times (64 times) 1 0 1 0 8 times (128 times) 4 rn0 0 1 0 0 16 times (256 times) 1 3 sn3 0 sn3 sn2 sn1 sn0 number of times hsync detected 1 0 0 0 0 not detected 2 sn2 0 0 0 0 1 32 times 1 0 0 1 0 64 times 1 sn1 0 0 1 0 0 128 times 1 1 0 0 0 256 times 0 sn0 0 1 external sync signal detection control recognition of the transition from the no signal state to the signal present state. sets the sampling period in which the sync signal can be detected continuously in the horizontal sync signal period (1h). the values in parentheses apply when rne0 (com51) is 1. external sync signal detection control recognition of the transition from the signal present state to the no signal state. sets the sampling period time in which the sync signal cannot be detected continuously in the horizontal sync signal period (1h).
no. 6526-21/38 lc74731w,74732w command51 (sync signal detection 2 setup command) first byte da0 to 7 register content notes state function 7 1 command 5 identification code 6 1 display control settings 50 41 3 0 extended command 1 identification code 21 1 mut1 0 mut1 mut0 output video signal output muting function selection 1 0 0 csync valid when the mute pin is low. 0 mut0 001pe 1 1 0 a0-17 ? second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 0 sync signal no signal to signal present discrimination - normal 5 rne0 values 1 sync signal no signal to signal present discrimination - values shown in parentheses 4 sjns3 0 sjns3 sjns2 sjns1 times 1 0 0 0 none 3 sjns2 00014 10108 001116 10032 2 sjns1 1 10164 1 1 0 128 1 1 1 256 1 sjcs1 0 sjcs1 sjcs0 pal ntsc 1 0 0 677 ns (1/3) 558 ns (1/2) 0 sjcs0 0 0 1 903 ns (1/4) 838 ns (1/3) 1 1 0 450 ns (1/2) 1117 ns (1/4) noise ignoring circuit setting for sync signal recognition for the no signal to signal present transition if more than the number of horizontal signals shown at the left are input during a 1h period, the circuit recognizes a no signal state. synchronization discrimination selects the clock used to delimit the hsyni signal. changes the judgment criterion values for sync signal recognition for the no signal to signal present transition. (com50)
no. 6526-22/38 lc74731w,74732w command52 (display control setup command) first byte da0 to 7 register content notes state function 7 1 command 5 identification code 6 1 display control settings 50 41 3 1 extended command 2 identification code 20 1 evebss 0 normal switches the enbvi signal 1 always high 0 lspss 0 normal lcstop control signal 1 ht12 ?n? ht34 ?ff second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 cinsel 0 blank area (the logical or of the character and outlining signals) switches the cv cr on state signal 1 video signal display area 5 cinctl 0cv cr : off cv cr on/off switching 1cv cr : on 4 vnpsel 0 v signal falling edges detected switches the v signal acquisition polarity when 1 v signal rising edges detected external mode/internal v separation is used 3 vspsel 0 vsep: about 8.9 ? (ntsc) switches the internal vertical separation time 1 vsep: about 17.8 ? (ntsc) 2 mskers 0 mask enabled clears the hsync and vsync masks 1 mask disabled 1 msksel 0 3h (ntsc) switches the vsync mask 1 20h (ntsc) 0 egl 0 outlining level 0 only (vbk0) switches the outlining level (only valid when blk0 1 two-stage outlining level (vbk0, vbk1) is 0 and blk1 is 1.)
no. 6526-23/38 lc74731w,74732w command53 (display control setup command) first byte da0 to 7 register content notes state function 7 1 command 5 identification code 6 1 display control settings 50 41 3 1 extended command 3 identification code 21 1 rslg1 0 rslg1 rslg0 switches the screen background color level 1 0 0 no1 rs1 0 rdlg0 0 0 1 no2 rs2 1 1 0 no3 rs3 second byte note that all registers are set to 0 when these ics are reset by the rst pin. synin: cvideo (built-in sync separator circuit) synin: hsync sepin: none (internal vertical separation) sepin: vsync or :vsync synin: hd synin: csync (internal vertical separation) sepin: csync (internal vertical separation) sepin: none da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 ctl3 0 internal vertical separation circuit switches the vsync signal input 1 external input 4 sp0sel 0 csync (sync separator output) switches the sepout pin output 1 halftone output 3 palal4 0 normal 1 always use 4 fsc timing (pal) 2 ihsel 0 synin pin input signal switches the internal vertical separation input 1 sepin pin input signal signal 1 vssel 0 negative polarity switches the sepin input polarity 1 positive polarity 0 hssel 0 negative polarity switches the synin input polarity (invalid for 1 positive polarity cvideo input)
no. 6526-24/38 lc74731w,74732w command60 (outlining control setup command) first byte da0 to 7 register content notes state function 7 1 command 6 identification code 6 1 display control settings 51 40 3 0 extended command 0 identification code 20 10 0 brm 0 normal mode specifies continuous mode 1 continuous mode second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 6 bxblv1 0 bxblv1 bxblv0 character frame - black level specification 1 0 0 no1 bk1 in line units 5 bxblv0 0 0 1 no2 bk2 1 1 0 no3 bk3 4 bxwlv1 0 bxwlv1 bxwlv0 character frame - white level specification 1 0 0 no1 cha1 in line units 3 bxwlv0 0 0 1 no2 cha2 1 1 0 no3 cha3 2 atsel 0 reverse video, blinking setup for the at1 and at2 function 1 character frame specified in line units 1 blk1 0 blk1 blk0 mode outlining mode specification 1 0 0 normal in line units 0 0 1 character size 0 blk0 1 1 0 outlining size 1 1 full area size
no. 6526-25/38 lc74731w,74732w command61 (outlining control and line specification setup command) first byte da0 to 7 register content notes state function 7 1 command 6 identification code 6 1 display control settings 51 40 3 0 extended command 1 identification code 21 10 0 lfcud 0 lower lines (0 to 5 (hexadecimal)) outlining control line specification 1 upper lines (6 to b (hexadecimal)) second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 lfcb5 0 line 6 (line 12) setting: off outlining line setting 1 line 6 (line 12) setting: on the values in parentheses apply when lfcud is 1. 4 lfca4 0 line 5 (line 11) setting: off 1 line 5 (line 11) setting: on 3 lfc93 0 line 4 (line 10) setting: off 1 line 4 (line 10) setting: on 2 lfc82 0 line 3 (line 9) setting: off 1 line 3 (line 9) setting: on 1 lfc71 0 line 2 (line 8) setting: off 1 line 2 (line 8) setting: on 0 lfc60 0 line 1 (line 7) setting: off 1 line 1 (line 7) setting: on
no. 6526-26/38 lc74731w,74732w command62 (line spacing control setup command) first byte da0 to 7 register content notes state function 7 1 command 6 identification code 6 1 display control settings 51 40 3 1 extended command 2 identification code 20 10 0 grm 0 normal mode continuous mode specification 1 continuous mode second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 bxc1 0 display outside the character area box left/right display specification 1 forces display within the character area in line units 4 gs1 0 gs1 gs0 mode in line units 1 0 0 normal (character background color) 0 0 1 full area and reverse invalid (other than ?) 3 gs0 1 1 0 transparent 1 (all) 1 1 transparent 2 (other than ?) 2 gy2 0 gy2 gy1 gy0 line spacing in line units 10000 1 gy1 00011 10102 00113 1004 0 gy0 1 1015 1106 1117
no. 6526-27/38 lc74731w,74732w command63 (line spacing control - line specification setup command) first byte da0 to 7 register content notes state function 7 1 command 6 identification code 6 1 display control settings 51 40 3 1 extended command 3 identification code 21 10 0 lgyud 0 lower lines (0 to 5 (hexadecimal)) line spacing control - line specification 1 upper lines (6 to b (hexadecimal)) second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 lgyb5 0 line 6 (line 12) setting: off line setting for line spacing control 1 line 6 (line 12) setting: on the values in parentheses apply when lgyud is 1. 4 lgya4 0 line 5 (line 11) setting: off 1 line 5 (line 11) setting: on 3 lgy93 0 line 4 (line 10) setting: off 1 line 4 (line 10) setting: on 2 lgy82 0 line 3 (line 9) setting: off 1 line 3 (line 9) setting: on 1 lgy71 0 line 2 (line 8) setting: off 1 line 2 (line 8) setting: on 0 lgy60 0 line 1 (line 7) setting: off 1 line 1 (line 7) setting: on
no. 6526-28/38 lc74731w,74732w command70 (display control setup command) first byte da0 to 7 register content notes state function 7 1 command 7 identification code 6 1 display control settings 51 41 3 0 extended command 0 identification code 20 10 0 lrm 0 normal mode continuous mode specification 1 continuous mode second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 bklc1 0 bklc1 bklc0 character color and character background color: 1 0 0 no1 bk1 black level specification 4 bklc0 0 0 1 no2 bk2 in line units 1 1 0 no3 bk3 3 chlc1 0 chlc1 chlc0 character color and character background color: 1 0 0 no1 cha1 white level specification 2 chlc0 0 0 1 no2 cha2 in line units 1 1 0 no3 cha3 1 rslc2 0 rslc1 rslc0 character color and character background color: 1 0 0 no1 rs1 color level specification 0 rslc1 0 0 1 no2 rs2 in line units 1 1 0 no3 rs3
no. 6526-29/38 lc74731w,74732w command71 (display levels - line specification setup command) first byte da0 to 7 register content notes state function 7 1 command 7 identification code 6 1 display control settings 51 41 3 0 extended command 1 identification code 21 10 0 lclud 0 lower lines (0 to 5 (hexadecimal)) display levels - line specification 1 upper lines (6 to b (hexadecimal)) second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 lclb5 0 line 6 (line 12) setting: off display level line setting 1 line 6 (line 12) setting: on the values in parentheses apply when lclud is 1. 4 lcla4 0 line 5 (line 11) setting: off 1 line 5 (line 11) setting: on 3 lcl93 0 line 4 (line 10) setting: off 1 line 4 (line 10) setting: on 2 lcl82 0 line 3 (line 9) setting: off 1 line 3 (line 9) setting: on 1 lcl71 0 line 2 (line 8) setting: off 1 line 2 (line 8) setting: on 0 lcl60 0 line 1 (line 7) setting: off 1 line 1 (line 7) setting: on
no. 6526-30/38 lc74731w,74732w command72 (halftone - line specification setup command) first byte da0 to 7 register content notes state function 7 1 command 7 identification code 6 1 display control setup 51 41 3 1 extended command 2 identification code 20 1 lhtdat 0 halftone: off halftone control 1 halftone: on 0 lhtud 0 lower lines (0 to 5 (hexadecimal)) halftone line specification 1 upper lines (6 to b (hexadecimal)) second byte note that all registers are set to 0 when these ics are reset by the rst pin. da0 to 7 register content notes state function 7 0 second byte identification bit 60 5 lhtb5 0 line 6 (line 12) setting: off halftone line setting 1 line 6 (line 12) setting: on the values in parentheses apply when lhtud is 1. 4 lhta4 0 line 5 (line 11) setting: off 1 line 5 (line 11) setting: on 3 lht93 0 line 4 (line 10) setting: off 1 line 4 (line 10) setting: on 2 lht82 0 line 3 (line 9) setting: off 1 line 3 (line 9) setting: on 1 lht71 0 line 2 (line 8) setting: off 1 line 2 (line 8) setting: on 0 lht60 0 line 1 (line 7) setting: off 1 line 1 (line 7) setting: on
no. 6526-31/38 lc74731w,74732w command73 (rgb control setup command) first byte da0 to 7 register content notes state function 7 1 command 7 identification code 6 1 display control setup 51 41 3 1 extended command 3 identification code 21 10 00 second byte da0 to 7 register content notes state function 7 0 second byte identification bit 6 dasss 0 normal switches the xtalin amplifier input 1 clkd = clkx only valid when rgb output is specified. 0 background color: off switches the background color in rgb output mode 5 gbsel 1 background color: on the background color is specified by com4 second byte. 4 outsel 0 switches the p9 to p12 outputs 1 rgb output switching the logical or with the outmod input. 3 hspsw 0 internal sync separator used switches the synin input 1 internal sync separator not used the logical or with the outmod input. 2 xonss 0 operation depends on the ctrl1 pin enables or disables the feedback resistor for the 1 feedback resistor disconnected xtalin clock. 1 blk02 0 blk01 blk00 switches the blkout output 1 0 0 cha + bk + chab box is always on. 0 0 1 cha +bk only always on when gbsel = 1. 0 blk01 1 1 0 cha only 1 1 bk only
display screen structure the display consists of 12 lines of 24 characters. up to 288 characters can be displayed. the number of characters that can be displayed is less than the 288 maximum when enlarged characters are displayed. display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. display screen structure (display memory addresses) no. 6526-32/38 lc74731w,74732w 24 characters 00 00 01 02 03 04 05 06 07 08 09 10 11 0 1 2 3 4 5 6 7 8 9 a b hex 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 hex 12 rows
composite video signal output levels (internally generated levels) ?cvout output level waveform (v dd 2 = 5.00 v) no. 6526-33/38 lc74731w,74732w 1h v bk1 v bk2 v cbl [v] 3.30 3.00 2.80 3.15 2.85 2.65 2.87 2.57 2.37 2.58 2.28 2.08 2.51 2.21 2.01 2.17 1.87 1.67 2.02 1.72 1.52 2.00 1.70 1.50 1.87 1.57 1.37 1.73 1.43 1.23 1.67 1.27 1.07 1.40 1.00 0.80 ? - ? v sn v cbh v rsh3 v rsh2 v pd v rsl1 v cha1 v cha2 v cha3 v bk3 v rsh1 v rsl3 v rsl2 output level output voltage (1) [v] output voltage (2) [v] output voltage (3) [v] v cha1 : character 1 2.65 2.85 3.25 v rsh2 : background color 2: high 2.37 2.57 2.97 v cha3 : character 3 2.23 2.43 2.83 v bk3 : outlining: 3 2.08 2.28 2.68 v rsh1 : background color 1: high 2.01 2.21 2.61 v bk2 : outlining: 2 1.80 2.00 2.40 v cbh : color burst: high 1.67 1.87 2.27 v rsl1 : background color 1: low 1.52 1.72 2.12 v bk1 : outlining: 1 1.50 1.70 2.10 v pd : pedestal 1.37 1.57 1.97 v rsl2 : background color 2: low 1.23 1.43 1.83 v cbl : color burst: low 1.07 1.27 1.67 v sn : sync 0.80 1.00 1.40 bcol01: rsl1 bcol0: cbh bcol11:rsh1
no. 6526-34/38 lc74731w,74732w yout output level waveform (v dd 2 = 5.00 v) bcol01: ybk1 bcol10: yrs1 bcol11: yrs3 [v] ? - ? 1.40 1.00 0.80 1.87 1.57 1.37 2.00 1.70 1.50 2.58 2.28 2.08 3.15 2.85 2.65 3.30 3.00 2.80 1h y sn y pd y cb y rs2 y bk2 y bk3 y rs3 y rs1 y cha1 y cha2 y cha3 y bk1 output level output voltage (1) [v] output voltage (2) [v] output voltage (3) [v] y cha1 : character 1 2.65 2.85 3.25 y cha2 : character 2 2.37 2.57 2.97 y cha3 : character 3 2.23 2.43 2.83 y bk3 : outlining: 3 2.08 2.28 2.68 y rs3 : background color 3 2.02 2.22 2.62 y rs2 : background color 2 1.80 2.00 2.40 y rs1 : background color 1 1.76 1.96 2.36 y bk1 : outlining: 1 1.50 1.70 2.10 y cb : color burst 1.37 1.57 1.97 y pd : pedestal 1.37 1.57 1.97 y sn : sync 0.80 1.00 1.40
no. 6526-35/38 lc74731w,74732w ?cout output level waveform (v dd 2 = 5.00 v) bcol01, 10, 11: cbias ccbh cbias 2.50 v ccbl crsl3 crsl2 crsh2 crsl1 crsh1 output level output voltage (1) [v] output voltage (2) [v] output voltage (3) [v] c rsh2 : background color 2: high 3.07 3.07 3.07 c cbh : color burst: high 2.80 2.80 2.80 c rsh1 : background color 1: low 2.74 2.74 2.74 c bias : bias 2.50 2.50 2.50 c rsl1 : background color 2: low 2.25 2.25 2.25 c cbl : color burst: low 2.20 2.20 2.20 c rsl2 : background color 2: low 1.93 1.93 1.93
sample application circuit ?cvideo, y/c no. 6526-36/38 lc74731w,74732w v ss 1 a6 d0 d1 d2 d3 d4 d5 d6 d7 ce oe a0 a1 a2 a3 a4 a5 v dd 2 cout nc cin cbias nc yout nc yin v ss 2 cvout nc cvin cvcr hftin synin 148 to external rom from external rom 33 16 32 17 +5 v buffer clamp clamp buffer clamp buffer 64 49 xtal in xtal out ctrl1 oscin oscout mute cdlr syncjdg/rout chara/gout blank/bout ibout/blkout outmod cs sin sclk a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 v dd 1 rst sepin sepout
no. 6526-37/38 lc74731w,74732w ?rgb v ss 1 a6 d0 d1 d2 d3 d4 d5 d6 d7 ce oe a0 a1 a2 a3 a4 a5 v dd 2 cout nc cin cbias nc yout nc yin v ss 2 cvout nc cvin cvcr hftin synin 148 to external rom from external rom 33 16 32 17 +5 v 64 49 xtal in xtal out ctrl1 oscin oscout mute cdlr syncjdg/rout chara/gout blank/bout ibout/blkout outmod vsync hsync cs sin sclk a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 v dd 1 rst sepin sepout
ps no. 6526-38/38 lc74731w,74732w this catalog provides information as of june, 2000. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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